]> git.ipfire.org Git - thirdparty/qemu.git/commit
hw/cxl: Standardize all references on CXL r3.1 and minor updates
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Fri, 26 Jan 2024 12:16:36 +0000 (12:16 +0000)
committerMichael S. Tsirkin <mst@redhat.com>
Wed, 14 Feb 2024 11:09:33 +0000 (06:09 -0500)
commit8700ee15de465a55e5c7281f87618ca4b4827441
tree2c1c753715d9d76e17ee12220f3a0ddbe8a8e93f
parent202f651469b7a6440577cb6a985cf1eb538ea899
hw/cxl: Standardize all references on CXL r3.1 and minor updates

Previously not all references mentioned any spec version at all.
Given r3.1 is the current specification available for evaluation at
www.computeexpresslink.org update references to refer to that.
Hopefully this won't become a never ending job.

A few structure definitions have been updated to add new fields.
Defaults of 0 and read only are valid choices for these new DVSEC
registers so go with that for now.

There are additional error codes and some of the 'questions' in
the comments are resolved now.

Update documentation reference to point to the CXL r3.1 specification
with naming closer to what is on the cover.

For cases where there are structure version numbers, add defines
so they can be found next to the register definitions.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126121636.24611-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
14 files changed:
docs/system/devices/cxl.rst
hw/cxl/cxl-component-utils.c
hw/cxl/cxl-device-utils.c
hw/cxl/cxl-events.c
hw/cxl/cxl-mailbox-utils.c
hw/mem/cxl_type3.c
hw/pci-bridge/cxl_downstream.c
hw/pci-bridge/cxl_root_port.c
hw/pci-bridge/cxl_upstream.c
include/hw/cxl/cxl_cdat.h
include/hw/cxl/cxl_component.h
include/hw/cxl/cxl_device.h
include/hw/cxl/cxl_events.h
include/hw/cxl/cxl_pci.h