]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: Use 32 bits for misa extensions
authorAnton Johansson <anjo@rev.ng>
Wed, 1 Oct 2025 07:32:34 +0000 (09:32 +0200)
committerPhilippe Mathieu-Daudé <philmd@linaro.org>
Thu, 16 Oct 2025 15:07:52 +0000 (17:07 +0200)
commit89e1cd7363e0a066a6b7a6059998efa3a89cc1b9
tree7e061a74fea5ce8d27598a64e5a4d06a61af742f
parentd936261844f68a07a3c51db08278eda273457d94
target/riscv: Use 32 bits for misa extensions

uint32_t is already in use in most places storing misa extensions such
as CPUArchState::misa_exts, RISCVCPUProfile::misa_exts,
RISCVImpliedExtsRule::implied_misa_exts.  Additionally. the field is
already migrated as uint32_t.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20251001073306.28573-2-anjo@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/riscv/cpu.h