clk: tegra: Add DFLL DVCO reset control for Tegra114

clk: tegra: Add DFLL DVCO reset control for Tegra114

The DVCO present in the DFLL IP block has a separate reset line, exposed
via the CAR IP block.  This reset line is asserted upon SoC reset.
Unless something (such as the DFLL driver) deasserts this line, the DVCO
will not oscillate, although reads and writes to the DFLL IP block will
complete.

Based on a3c83ff2 ("clk: tegra: Add DFLL DVCO reset control for Tegra124")

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>