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RISC-V: Add sifive-p450, sifive-p67 to -mcpu
authorMonk Chiang <monk.chiang@sifive.com>
Fri, 2 Feb 2024 03:58:45 +0000 (11:58 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Mon, 5 Feb 2024 02:06:38 +0000 (18:06 -0800)
commit91e09b3a7e9c86bb29fc138744fd2e087216733c
tree544c71ca0d9bc46bb4fa4145c16727459ddc79detree
parent7c190f93cd53a8391d78da2ba39d98dba9211faacommit | diff
RISC-V: Add sifive-p450, sifive-p67 to -mcpu

gcc/ChangeLog:

* config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
* doc/invoke.texi (RISC-V Options): Add sifive-p450,
sifive-p670.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/mcpu-sifive-p450.c: New test.
* gcc.target/riscv/mcpu-sifive-p670.c: New test.
gcc/config/riscv/riscv-cores.def diff | blob | blame | history
gcc/doc/invoke.texi diff | blob | blame | history
gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c [new file with mode: 0644] blob
Mirror of https://gcc.gnu.org/git/gcc.git