RISC-V: Add testcases for form 4 of scalar signed SAT_SUB

RISC-V: Add testcases for form 4 of scalar signed SAT_SUB

Form 4:
  #define DEF_SAT_S_SUB_FMT_4(T, UT, MIN, MAX)           \
  T __attribute__((noinline))                            \
  sat_s_sub_##T##_fmt_4 (T x, T y)                       \
  {                                                      \
    T minus;                                               \
    bool overflow = __builtin_sub_overflow (x, y, &minus); \
    return !overflow ? minus : x < 0 ? MIN : MAX;          \
  }

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_s_sub-4-i16.c: New test.
	* gcc.target/riscv/sat_s_sub-4-i32.c: New test.
	* gcc.target/riscv/sat_s_sub-4-i64.c: New test.
	* gcc.target/riscv/sat_s_sub-4-i8.c: New test.
	* gcc.target/riscv/sat_s_sub-run-4-i16.c: New test.
	* gcc.target/riscv/sat_s_sub-run-4-i32.c: New test.
	* gcc.target/riscv/sat_s_sub-run-4-i64.c: New test.
	* gcc.target/riscv/sat_s_sub-run-4-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>