RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = max -1.

RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = max -1.

form 1:
T __attribute__((noinline))             \
sat_u_sub_imm##IMM##_##T##_fmt_1 (T y)  \
{                                       \
  return (T)IMM >= y ? (T)IMM - y : 0;  \
}

Passed the rv64gcv regression test.

Change-Id: Idaa1ab41f2a5785112279ea8ee2c93236457b740
Signed-off-by: Li Xu <xuli1@eswincomputing.com>
gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_u_sub_imm-1_3.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-2_3.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-3_3.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-4_1.c: New test.