]> git.ipfire.org Git - thirdparty/gcc.git/commit
aarch64: PR target/99195 annotate simple ternary ops for vec-concat with zero
authorKyrylo Tkachov <kyrylo.tkachov@arm.com>
Thu, 4 May 2023 08:42:37 +0000 (09:42 +0100)
committerKyrylo Tkachov <kyrylo.tkachov@arm.com>
Thu, 4 May 2023 08:43:17 +0000 (09:43 +0100)
commit93c26deab98fc80b616a1c53c324a88f61036f53
tree0465b097cafe1a4bce8e0fac662bcdbd0828a2ac
parentd840bc5cab39aa3dd8222d72b2cd40942bf91c93
aarch64: PR target/99195 annotate simple ternary ops for vec-concat with zero

We're now moving onto various simple ternary instructions, including some lane forms.
These include intrinsics that map down to mla, mls, fma, aba, bsl instructions.
Tests are added for lane 0 and lane 1 as for some of these instructions the lane 0 variants
use separate simpler patterns that need a separate annotation.

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<su>aba<mode>): Rename to...
(aarch64_<su>aba<mode><vczle><vczbe>): ... This.
(aarch64_mla<mode>): Rename to...
(aarch64_mla<mode><vczle><vczbe>): ... This.
(*aarch64_mla_elt<mode>): Rename to...
(*aarch64_mla_elt<mode><vczle><vczbe>): ... This.
(*aarch64_mla_elt_<vswap_width_name><mode>): Rename to...
(*aarch64_mla_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
(aarch64_mla_n<mode>): Rename to...
(aarch64_mla_n<mode><vczle><vczbe>): ... This.
(aarch64_mls<mode>): Rename to...
(aarch64_mls<mode><vczle><vczbe>): ... This.
(*aarch64_mls_elt<mode>): Rename to...
(*aarch64_mls_elt<mode><vczle><vczbe>): ... This.
(*aarch64_mls_elt_<vswap_width_name><mode>): Rename to...
(*aarch64_mls_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
(aarch64_mls_n<mode>): Rename to...
(aarch64_mls_n<mode><vczle><vczbe>): ... This.
(fma<mode>4): Rename to...
(fma<mode>4<vczle><vczbe>): ... This.
(*aarch64_fma4_elt<mode>): Rename to...
(*aarch64_fma4_elt<mode><vczle><vczbe>): ... This.
(*aarch64_fma4_elt_<vswap_width_name><mode>): Rename to...
(*aarch64_fma4_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
(*aarch64_fma4_elt_from_dup<mode>): Rename to...
(*aarch64_fma4_elt_from_dup<mode><vczle><vczbe>): ... This.
(fnma<mode>4): Rename to...
(fnma<mode>4<vczle><vczbe>): ... This.
(*aarch64_fnma4_elt<mode>): Rename to...
(*aarch64_fnma4_elt<mode><vczle><vczbe>): ... This.
(*aarch64_fnma4_elt_<vswap_width_name><mode>): Rename to...
(*aarch64_fnma4_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
(*aarch64_fnma4_elt_from_dup<mode>): Rename to...
(*aarch64_fnma4_elt_from_dup<mode><vczle><vczbe>): ... This.
(aarch64_simd_bsl<mode>_internal): Rename to...
(aarch64_simd_bsl<mode>_internal<vczle><vczbe>): ... This.
(*aarch64_simd_bsl<mode>_alt): Rename to...
(*aarch64_simd_bsl<mode>_alt<vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

PR target/99195
* gcc.target/aarch64/simd/pr99195_3.c: New test.
gcc/config/aarch64/aarch64-simd.md
gcc/testsuite/gcc.target/aarch64/simd/pr99195_3.c [new file with mode: 0644]