]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: zicfilp `lpad` impl and branch tracking
authorDeepak Gupta <debug@rivosinc.com>
Tue, 8 Oct 2024 22:49:57 +0000 (15:49 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 30 Oct 2024 01:22:08 +0000 (11:22 +1000)
commit966f3a38958acf18ae64031c014dcd58e2181211
treee5215324a5cecb49f4edb0e862b7ae787801144c
parentb039c9611331ccf61a53b2d26d80a8cfb596e0ce
target/riscv: zicfilp `lpad` impl and branch tracking

Implements setting lp expected when `jalr` is encountered and implements
`lpad` instruction of zicfilp. `lpad` instruction is taken out of
auipc x0, <imm_20>. This is an existing HINTNOP space. If `lpad` is
target of an indirect branch, cpu checks for 20 bit value in x7 upper
with 20 bit value embedded in `lpad`. If they don't match, cpu raises a
sw check exception with tval = 2.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-8-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_user.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvi.c.inc