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riscv64: Fix IR generation for shift operations (BZ 509157)
authorFlorian Krohm <flo2030@eich-krohm.de>
Tue, 30 Sep 2025 20:14:24 +0000 (20:14 +0000)
committerFlorian Krohm <flo2030@eich-krohm.de>
Tue, 30 Sep 2025 20:14:24 +0000 (20:14 +0000)
commit97831bbbc208f3c574095770aff9b19e5a2c6aae
tree888f3ec601df5b36d336ea7945d9b749dea4f2f3tree | snapshot
parenta984b14036fce483f98ece084c4d54370749fd26commit | diff
riscv64: Fix IR generation for shift operations  (BZ 509157)

For SLL, SRL, and SRA the shift amount is 6 bits wide - not 8 bits.
For SLLW, SRLW, and SRAW the shift amount is 5 bits wide - not 8 bits.

Patch for IR generation by Christoph Jung (christoph.j27@googlemail.com).

Also clarify semantics of bitwise shift operators in libvex_ir.h

Fixes https://bugs.kde.org/show_bug.cgi?id=509157
VEX/priv/guest_riscv64_toIR.c diff | blob | blame | history
VEX/pub/libvex_ir.h diff | blob | blame | history
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