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target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions
authorSiarhei Volkau <lis8215@gmail.com>
Thu, 8 Jun 2023 10:42:05 +0000 (13:42 +0300)
committerPhilippe Mathieu-Daudé <philmd@linaro.org>
Mon, 10 Jul 2023 21:33:38 +0000 (23:33 +0200)
commit98db7a585eb402579d2e5a7ec2b04fa22d12490a
tree7ef67027c576ee5916da2437a6808b03896cd734tree
parent9e51e0cd4bac9dd94f593d66497f635edd871d2ecommit | diff
target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions

These instructions are all dual 32-bit addition/subtraction in
various combinations. The instructions are grouped in pool12,
see the opcode organization in the file.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-17-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/mips/tcg/mxu_translate.c diff | blob | blame | history
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