RISC-V: Support VLS shift vectorization

RISC-V: Support VLS shift vectorization

After this patch, this following case will be well optimized:

  void __attribute__ ((noinline, noclone))                                     \
  PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c)  \
  {                                                                            \
    for (int i = 0; i < NUM; ++i)                                              \
      a[i] = b[i] OP c[i];                                                     \
  }

DEF_OP_VV (shift, 16, int32_t, >>)

ASM:
shift_int32_t16:
	vsetivli	zero,16,e32,mf2,ta,ma
	vle32.v	v1,0(a1)
	vle32.v	v2,0(a2)
	vsra.vv	v1,v1,v2
	vse32.v	v1,0(a0)
	ret

gcc/ChangeLog:

	* config/riscv/autovec.md: Add VLS shift.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS shift.
	* gcc.target/riscv/rvv/autovec/vls/shift-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/shift-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/shift-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/shift-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/shift-5.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/shift-6.c: New test.