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author	Sachin Monga <smonga@linux.ibm.com>
	Tue, 7 Oct 2025 08:17:00 +0000 (03:17 -0500)
committer	Sachin Monga <smonga@linux.ibm.com>
	Tue, 7 Oct 2025 08:20:44 +0000 (03:20 -0500)
commit	9a40b1cda519cc4f532acb6d020390829df3d81b
tree	9fd55d53b83646e7bab6bafbe06dfb8f611361f5	tree \| snapshot
parent	fcfbc3ee310519f600b712c699e2f411c6a5c7d6	commit \| diff

ppc64le: Restore optimized strcmp for power10

This patch addresses the actual cause of CVE-2025-5702

The vector non-volatile registers are not used anymore for
32 byte load and comparison operation

Additionally, the assembler workaround used earlier for the
instruction lxvp is replaced with actual instruction.

Signed-off-by: Sachin Monga <smonga@linux.ibm.com>
Co-authored-by: Paul Murphy <paumurph@redhat.com>

sysdeps/powerpc/powerpc64/le/power10/strcmp.S	[new file with mode: 0644]	blob
sysdeps/powerpc/powerpc64/multiarch/Makefile		diff \| blob \| blame \| history
sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c		diff \| blob \| blame \| history
sysdeps/powerpc/powerpc64/multiarch/strcmp-power10.S	[new file with mode: 0644]	blob
sysdeps/powerpc/powerpc64/multiarch/strcmp.c		diff \| blob \| blame \| history

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