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RISC-V: Fine tune gather load RA constraint
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Mon, 13 Mar 2023 08:28:55 +0000 (16:28 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Wed, 26 Apr 2023 03:57:51 +0000 (11:57 +0800)
commita010f0e08501b267ecb925ff88450f58e01dd991
treeff5e5e075d410397f6eb3714032053c248a6a487tree
parenta8d5e14f524283484c2a466353f92f7eaadae9f7commit | diff
RISC-V: Fine tune gather load RA constraint

For DEST EEW < SOURCE EEW, we can partial overlap register
according to RVV ISA.

gcc/ChangeLog:

* config/riscv/vector.md: Fix RA constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/narrow_constraint-12.c: New test.
gcc/config/riscv/vector.md diff | blob | blame | history
gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-12.c [new file with mode: 0644] blob
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