]> git.ipfire.org Git - thirdparty/linux.git/commit
dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) TSA controller
authorHerve Codina <herve.codina@bootlin.com>
Thu, 8 Aug 2024 07:11:00 +0000 (09:11 +0200)
committerChristophe Leroy <christophe.leroy@csgroup.eu>
Tue, 3 Sep 2024 05:49:18 +0000 (07:49 +0200)
commita0bbe77fafbc7e5eb41fbf3dc5cdb3608d8778a3
tree38919a8e688878c5b25288b3f5293c8644d8578d
parenta68757abc0d5df7142720d030276f9693e4958af
dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) TSA controller

Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.

This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM TSA, this QE TSA can handle
up to 4 TDMs instead of 2 and allows to configure the logic level of
sync signals.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-8-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml [new file with mode: 0644]
include/dt-bindings/soc/qe-fsl,tsa.h [new file with mode: 0644]