RISC-V: Support IMM for operand 1 of ussub pattern

RISC-V: Support IMM for operand 1 of ussub pattern

This patch would like to allow IMM for the operand 1 of ussub pattern.
Aka .SAT_SUB(x, 22) as the below example.

Form 2:
  #define DEF_SAT_U_SUB_IMM_FMT_2(T, IMM) \
  T __attribute__((noinline))             \
  sat_u_sub_imm##IMM##_##T##_fmt_2 (T x)  \
  {                                       \
    return x >= (T)IMM ? x - (T)IMM : 0;  \
  }

DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1022)

It is almost the as support imm for operand 0 of ussub pattern, but
allow the second operand to be imm insted of the first operand.

The below test suites are passed for this patch:
1. The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_ussub): Gen xmode for the
	second operand, aka y in parameter.
	* config/riscv/riscv.md (ussub<mode>3): Allow const_int for operand 2.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_u_sub_imm-5.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-5_1.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-5_2.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-6.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-6_1.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-6_2.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-7.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-7_1.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-7_2.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-8.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-5.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-6.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-7.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>