RISC-V: Add testcases for scalar unsigned SAT_ADD form 4

RISC-V: Add testcases for scalar unsigned SAT_ADD form 4

After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC-V backend implement the scalar .SAT_ADD, add more test
case to cover the form 4 of unsigned .SAT_ADD.

Form 4:
  #define SAT_ADD_U_4(T) \
  T sat_add_u_4_##T (T x, T y) \
  { \
    T ret; \
    return __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test macro for form 4.
	* gcc.target/riscv/sat_u_add-17.c: New test.
	* gcc.target/riscv/sat_u_add-18.c: New test.
	* gcc.target/riscv/sat_u_add-19.c: New test.
	* gcc.target/riscv/sat_u_add-20.c: New test.
	* gcc.target/riscv/sat_u_add-run-17.c: New test.
	* gcc.target/riscv/sat_u_add-run-18.c: New test.
	* gcc.target/riscv/sat_u_add-run-19.c: New test.
	* gcc.target/riscv/sat_u_add-run-20.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>