RISC-V: Optimize TARGET_XTHEADCONDMOV

RISC-V: Optimize TARGET_XTHEADCONDMOV

This patch allows less instructions to be used when TARGET_XTHEADCONDMOV is enabled.

Provide an example from the existing testcases.

Testcase:
int ConEmv_imm_imm_reg(int x, int y){
  if (x == 1000) return 10;
  return y;
}

Cflags:
-O2 -march=rv64gc_xtheadcondmov -mabi=lp64d

before patch:
ConEmv_imm_imm_reg:
	addi	a5,a0,-1000
	li	a0,10
	th.mvnez	a0,zero,a5
	th.mveqz	a1,zero,a5
	or	a0,a0,a1
	ret

after patch:
ConEmv_imm_imm_reg:
	addi	a5,a0,-1000
	li	a0,10
	th.mvnez	a0,a1,a5
	ret

Signed-off-by: Die Li <lidie@eswincomputing.com>
gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_conditional_move_onesided):
	Delete.
	(riscv_expand_conditional_move):  Reuse the TARGET_SFB_ALU expand
	process for TARGET_XTHEADCONDMOV

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Update the output.
	* gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Likewise.