RISC-V: Handle case when constant vector construction target rtx is not a register

RISC-V: Handle case when constant vector construction target rtx is not a register

This manifests in RTL that is optimized away which causes runtime failures
in the testsuite. Update all patterns to use a temp result register if required.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector): Use tmp register if
	needed.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>