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doc: board: ti: am62x_sk: Add A53 SPL DDR layout
authorNikhil M Jain <n-jain1@ti.com>
Tue, 18 Jul 2023 08:57:35 +0000 (14:27 +0530)
committerTom Rini <trini@konsulko.com>
Fri, 21 Jul 2023 19:32:12 +0000 (15:32 -0400)
commita72532fa194ed31b559bdd8b287854df0a4903f8
treeb6981028f79b40cc7a85b8bb615704edcb23d66ftree | snapshot
parent1f7682383f4334afc21ea62b072392955d201d62commit | diff
doc: board: ti: am62x_sk: Add A53 SPL DDR layout

To understand usage of DDR in A53 SPL stage, add a table showing region
and space used by major components of SPL.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
doc/board/ti/am62x_sk.rst diff | blob | blame | history
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