]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Fix missing implied Zicsr from Zve32x
authorJerry Zhang Jian <jerry.zhangjian@sifive.com>
Wed, 30 Apr 2025 07:34:07 +0000 (15:34 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Wed, 30 Apr 2025 09:26:24 +0000 (17:26 +0800)
commita992164c2899735525a7a267654473b7e527ef0d
tree7716c1ef74e61c9e054dcd20753a612e698c62f6
parent83bb288faa39a0bf5ce2d62e21a090a130d8dda4
RISC-V: Fix missing implied Zicsr from Zve32x

The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-19.c: set the march to rv64im_zve32x
instead of rv64gc_zve32x to avoid Zicsr implied by g. Extra m is
added to avoid current 'V' extension requires 'M' extension

Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
gcc/common/config/riscv/riscv-common.cc
gcc/testsuite/gcc.target/riscv/predef-19.c