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AArch64: Improve codegen in AdvSIMD asinh
authorLuna Lamb <luna.lamb@arm.com>
Fri, 3 Jan 2025 19:00:12 +0000 (19:00 +0000)
committerWilco Dijkstra <wilco.dijkstra@arm.com>
Thu, 27 Feb 2025 17:07:30 +0000 (17:07 +0000)
commitabfd20ebbd2883f2c6e5f16709f7b9781c3c8068
tree070dad398ec32cd9e05f1a86dc1e2d5cacd247fftree
parentbf2b60a56036c951a798845223a2e04cc48507e4commit | diff
AArch64: Improve codegen in AdvSIMD asinh

Improves memory access and removes spills.
Load the polynomial evaluation coefficients into 2 vectors and use lanewise
MLAs.  Reduces MOVs 6->3 , LDR 11->5, STR/STP 2->0, ADRP 3->2.

(cherry picked from commit 140b985e5a2071000122b3cb63ebfe88cf21dd29)
sysdeps/aarch64/fpu/asinh_advsimd.c diff | blob | blame | history
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