RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = 1.

RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = 1.

form 1:
T __attribute__((noinline))             \
sat_u_sub_imm##IMM##_##T##_fmt_1 (T y)  \
{                                       \
  return (T)IMM >= y ? (T)IMM - y : 0;  \
}

Passed the rv64gcv regression test.

Change-Id: I8805225b445cdbbc685f4f54a4d66c7ee8f748e1
Signed-off-by: Li Xu <xuli1@eswincomputing.com>
gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_u_sub_imm-1_4.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-2_4.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-3_4.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-4_2.c: New test.