]> git.ipfire.org Git - thirdparty/gcc.git/commit
aarch64: Avoid hard-coding specific register allocations
authorRichard Sandiford <richard.sandiford@arm.com>
Tue, 9 May 2023 06:43:35 +0000 (07:43 +0100)
committerRichard Sandiford <richard.sandiford@arm.com>
Tue, 9 May 2023 06:43:35 +0000 (07:43 +0100)
commitaf84cb1f3e16965b0a18e2165cc1626b9d588c70
tree119cbe7602421c4e56a8105ad59441dae2807451
parent5c53d82582c5f24e8523f606088ca82b3778d069
aarch64: Avoid hard-coding specific register allocations

Some tests hard-coded specific allocations for temporary registers,
whereas the RA should be free to pick anything that doesn't force
unnecessary moves or spills.

gcc/testsuite/
* gcc.target/aarch64/asimd-mul-to-shl-sub.c: Allow any register
allocation for temporary results, rather than requiring specific
registers.
* gcc.target/aarch64/auto-init-padding-1.c: Likewise.
* gcc.target/aarch64/auto-init-padding-2.c: Likewise.
* gcc.target/aarch64/auto-init-padding-3.c: Likewise.
* gcc.target/aarch64/auto-init-padding-4.c: Likewise.
* gcc.target/aarch64/auto-init-padding-9.c: Likewise.
* gcc.target/aarch64/memset-corner-cases.c: Likewise.
* gcc.target/aarch64/memset-q-reg.c: Likewise.
* gcc.target/aarch64/simd/vaddlv_1.c: Likewise.
* gcc.target/aarch64/sve-neon-modes_1.c: Likewise.
* gcc.target/aarch64/sve-neon-modes_3.c: Likewise.
* gcc.target/aarch64/sve/load_scalar_offset_1.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6_256.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6_512.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6_1024.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6_2048.c: Likewise.
* gcc.target/aarch64/sve/pr89007-1.c: Likewise.
* gcc.target/aarch64/sve/pr89007-2.c: Likewise.
* gcc.target/aarch64/sve/store_scalar_offset_1.c: Likewise.
* gcc.target/aarch64/vadd_reduc-1.c: Likewise.
* gcc.target/aarch64/vadd_reduc-2.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_bf16.c: Allow the temporary
predicate register to be any of p4-p7, rather than requiring p4
specifically.
* gcc.target/aarch64/sve/pcs/args_5_be_f16.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_f32.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_f64.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_s8.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_s16.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_s32.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_s64.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_u8.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_u16.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_u32.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_5_be_u64.c: Likewise.
33 files changed:
gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c
gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c
gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c
gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c
gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c
gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c
gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c
gcc/testsuite/gcc.target/aarch64/memset-q-reg.c
gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c
gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c
gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c
gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c
gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c
gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c
gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c
gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c
gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c
gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c