]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: tracking indirect branches (fcfi) for zicfilp
authorDeepak Gupta <debug@rivosinc.com>
Tue, 8 Oct 2024 22:49:56 +0000 (15:49 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 30 Oct 2024 01:22:08 +0000 (11:22 +1000)
commitb039c9611331ccf61a53b2d26d80a8cfb596e0ce
treec734f6116db273a462ce2c842191d6ba02311f1e
parent6031102401ae8a69a87b20fbec2aae666625d96a
target/riscv: tracking indirect branches (fcfi) for zicfilp

zicfilp protects forward control flow (if enabled) by enforcing all
indirect call and jmp must land on a landing pad instruction `lpad`. If
target of an indirect call or jmp is not `lpad` then cpu/hart must raise
a sw check exception with tval = 2.

This patch implements the mechanism using TCG. Target architecture branch
instruction must define the end of a TB. Using this property, during
translation of branch instruction, TB flag = FCFI_LP_EXPECTED can be set.
Translation of target TB can check if FCFI_LP_EXPECTED flag is set and a
flag (fcfi_lp_expected) can be set in DisasContext. If `lpad` gets
translated, fcfi_lp_expected flag in DisasContext can be cleared. Else
it'll fault.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-7-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/cpu_helper.c
target/riscv/translate.c