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author	Julian Seward <jseward@acm.org>
	Sat, 22 Dec 2018 06:23:00 +0000 (07:23 +0100)
committer	Julian Seward <jseward@acm.org>
	Sat, 22 Dec 2018 06:23:00 +0000 (07:23 +0100)
commit	b078fabb56e34115e55357c319d589b9455dd189
tree	b965367521fee5bcfafe47961117f3327b651c36	tree \| snapshot
parent	6cb6bdbd0a38e9b5f5c4f676afb72a23b6bfb1b5	commit \| diff

amd64 pipeline: generate much better code for pshufb mm/xmm/ymm.  n-i-bz.

pshufb mm/xmm/ymm rearranges byte lanes in vector registers.  It's fairly
widely used, but we generated terrible code for it.  With this patch, we just
generate, at the back end, pshufb plus a bit of masking, which is a great
improvement.

12 files changed:

VEX/priv/guest_amd64_toIR.c		diff \| blob \| blame \| history
VEX/priv/host_amd64_defs.c		diff \| blob \| blame \| history
VEX/priv/host_amd64_defs.h		diff \| blob \| blame \| history
VEX/priv/host_amd64_isel.c		diff \| blob \| blame \| history
VEX/priv/host_generic_simd128.c		diff \| blob \| blame \| history
VEX/priv/host_generic_simd128.h		diff \| blob \| blame \| history
VEX/priv/host_generic_simd64.c		diff \| blob \| blame \| history
VEX/priv/host_generic_simd64.h		diff \| blob \| blame \| history
VEX/priv/ir_defs.c		diff \| blob \| blame \| history
VEX/pub/libvex_ir.h		diff \| blob \| blame \| history
memcheck/mc_translate.c		diff \| blob \| blame \| history
memcheck/tests/vbit-test/irops.c		diff \| blob \| blame \| history

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