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author	Kito Cheng <kito.cheng@sifive.com>
	Mon, 19 Dec 2022 09:28:25 +0000 (17:28 +0800)
committer	Kito Cheng <kito.cheng@sifive.com>
	Mon, 19 Dec 2022 09:39:33 +0000 (17:39 +0800)
commit	b346e77f4d7b482df78f119819b1e06a544ef515
tree	21c3821d832d39f8e7a950c7b58ddd8bbde4a71e	tree \| snapshot
parent	97a8e88cd7d22562c0ea4f73687d3c93c21e12fb	commit \| diff

RISC-V: Fix vwrite_csr.c and vread_csr.c

gcc/testsuite:

* gcc.target/riscv/rvv/base/vread_csr.c: Use specific option
instead.
* gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.

gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c		diff \| blob \| blame \| history
gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c		diff \| blob \| blame \| history

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