RISC-V: Add sifive-x280 to -mcpu

RISC-V: Add sifive-x280 to -mcpu

x280 is one of SiFive core, and it release for a while, also
upstream LLVM already support that.

[1] https://www.sifive.com/cores/intelligence-x280

gcc/ChangeLog:

	* config/riscv/riscv-cores.def: Add sifive-x280.
	* doc/invoke.texi (RISC-V Options): Add sifive-x280

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-sifive-x280.c: New test.