]> git.ipfire.org Git - thirdparty/gcc.git/commit
[PATCH] [RISC-V]Support -mcpu for Xuantie cpu
authorYixuan Chen <chenyixuan@iscas.ac.cn>
Tue, 22 Apr 2025 10:45:44 +0000 (04:45 -0600)
committerJeff Law <jlaw@ventanamicro.com>
Tue, 22 Apr 2025 10:56:02 +0000 (04:56 -0600)
commitbd8a48500c1e775ab9cb4a737314cb800444ab4b
treecc2fdd263824a9c902ced9615514ebd79aede3c7
parent1b1b3896a2a026188f0ce36df6cbb490ee89edb8
[PATCH] [RISC-V]Support -mcpu for Xuantie cpu

Support -mcpu=xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920, xt-c920v2
for Xuantie series cpu.
ref:https://www.xrvm.cn/community/download?id=4224248662731067392

without fmv_cost, vector_unaligned_access, use_divmod_expansion, overlap_op_by_pieces, fill the tune info with generic ooo for further modification.

gcc/ChangeLog:

* config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c908v,
xt-c910, xt-c910v2, xt-c920, xt-c920v2.
(RISCV_CORE): Add xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920,
xt-c920v2.
* doc/invoke.texi: Add xt-c908, xt-c908v, xt-c910, xt-c910v2,
xt-c920, xt-c920v2.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/mcpu-xt-c908.c: test -mcpu=xt-c908.
* gcc.target/riscv/mcpu-xt-c910.c: test -mcpu=xt-c910.
* gcc.target/riscv/mcpu-xt-c920v2.c: test -mcpu=xt-c920v2.
* gcc.target/riscv/mcpu-xt-c908v.c: test -mcpu=xt-c908v.
* gcc.target/riscv/mcpu-xt-c910v2.c: test -mcpu=xt-c910v2.
* gcc.target/riscv/mcpu-xt-c920.c: test -mcpu=xt-c920.
gcc/config/riscv/riscv-cores.def
gcc/doc/invoke.texi
gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c [new file with mode: 0644]