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(parent: fac5a07) | patch
target-mips: move PREF, CACHE, LLD and SCD instructions
authorLeon Alrae <leon.alrae@imgtec.com>
Fri, 27 Jun 2014 07:49:03 +0000 (08:49 +0100)
committerLeon Alrae <leon.alrae@imgtec.com>
Mon, 13 Oct 2014 11:38:24 +0000 (12:38 +0100)
commitbf7910c6b1bc47517a9d7a6049d97d056e014eb0
treee78c66baf97b61ac6540dbb2dd90aa580d5b8777tree
parentfac5a0733013f4e148b406056526f2208464d799commit | diff
target-mips: move PREF, CACHE, LLD and SCD instructions

The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
disas/mips.c diff | blob | blame | history
target-mips/translate.c diff | blob | blame | history
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