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RISC-V: Weaken mem_thread_fence
authorPatrick O'Neill <patrick@rivosinc.com>
Fri, 7 Apr 2023 17:44:09 +0000 (10:44 -0700)
committerPatrick O'Neill <patrick@rivosinc.com>
Tue, 2 May 2023 20:08:04 +0000 (13:08 -0700)
commitbff7c77386447936dd614ebc7086b826c99c6642
tree0d4ed8463e02c38fb2cbdd93477671e5723c68f2tree
parent942ab49b5f8955371cf5db23608ba5f5f5244152commit | diff
RISC-V: Weaken mem_thread_fence

This change brings atomic fences in line with table A.6 of the ISA
manual.

Relax mem_thread_fence according to the memmodel given.

2023-04-27 Patrick O'Neill <patrick@rivosinc.com>

gcc/ChangeLog:

* config/riscv/sync.md (mem_thread_fence_1): Change fence
depending on the given memory model.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
gcc/config/riscv/sync.md diff | blob | blame | history
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