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(parent: cd65e26) | patch
x86: fix CVT{,T}PD2PI insns
authorJan Beulich <jbeulich@suse.com>
Fri, 28 Jun 2019 08:46:56 +0000 (08:46 +0000)
committerJan Beulich <jbeulich@gcc.gnu.org>
Fri, 28 Jun 2019 08:46:56 +0000 (08:46 +0000)
commitc1a106c222804416897c53f3c5dc8f028137151e
treed3a1783b959c2a730bd4aa6c76316916d3eb4f78tree | snapshot
parentcd65e2652d2c38eaa63f01ccc3a60bb5225235d2commit | diff
x86: fix CVT{,T}PD2PI insns

With just an "m" constraint misaligned memory operands won't be forced
into a register, and hence cause #GP. So far this was guaranteed only
in the case that CVT{,T}PD2DQ were chosen (which looks to be the case on
x86-64 only).

Switch the second alternative to Bm and also replace
nonimmediate_operand by vector_operand.

From-SVN: r272780
gcc/ChangeLog diff | blob | blame | history
gcc/config/i386/sse.md diff | blob | blame | history
gcc/testsuite/ChangeLog diff | blob | blame | history
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