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drm/amdgpu: Correct se_num and reg_inst for gfx v9_4_3 ras counters
authorHawking Zhang <Hawking.Zhang@amd.com>
Wed, 6 Sep 2023 09:56:20 +0000 (17:56 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 6 Sep 2023 18:36:57 +0000 (14:36 -0400)
commitc2c23a10f18016baab5c8762f9bce5bf80cc6b8f
tree23925d8282b72d1fafa6360e95cb12f1f597d041tree | snapshot
parent1b8e56b994592fe8909fdf9d81674a9bf5947217commit | diff
drm/amdgpu: Correct se_num and reg_inst for gfx v9_4_3 ras counters

gfx_v9_4_3_ue|ce_reg_list is an array per gfx core instance
correct the settings of se_num and reg_inst for some of
gfx ras counters so all the available register instances
can be polled for ras status.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git