LoongArch: Fix FP vector comparsons [PR113034]

LoongArch: Fix FP vector comparsons [PR113034]

We had the following mappings between <x>vfcmp submenmonics and RTX
codes:

    (define_code_attr fcc
      [(unordered "cun")
       (ordered   "cor")
       (eq       "ceq")
       (ne       "cne")
       (uneq      "cueq")
       (unle      "cule")
       (unlt      "cult")
       (le       "cle")
       (lt       "clt")])

This is inconsistent with scalar code:

    (define_code_attr fcond [(unordered "cun")
                             (uneq "cueq")
                             (unlt "cult")
                             (unle "cule")
                             (eq "ceq")
                             (lt "slt")
                             (le "sle")
                             (ordered "cor")
                             (ltgt "sne")
                             (ne "cune")
                             (ge "sge")
                             (gt "sgt")
                             (unge "cuge")
                             (ungt "cugt")])

For every RTX code for which the LSX/LASX code is different from the
scalar code, the scalar code is correct and the LSX/LASX code is wrong.
Most seriously, the RTX code NE should be mapped to "cneq", not "cne".
Rewrite <x>vfcmp define_insns in simd.md using the same mapping as
scalar fcmp.

Note that GAS does not support [x]vfcmp.{c/s}[u]{ge/gt} (pseudo)
instruction (although fcmp.{c/s}[u]{ge/gt} is supported), so we need to
switch the order of inputs and use [x]vfcmp.{c/s}[u]{le/lt} instead.

The <x>vfcmp.{sult/sule/clt/cle}.{s/d} instructions do not have a single
RTX code, but they can be modeled as an inversed RTX code following a
"not" operation.  Doing so allows the compiler to optimized vectorized
__builtin_isless etc. to a single instruction.  This optimization should
be added for scalar code too and I'll do it later.

Tests are added for mapping between C code, IEC 60559 operations, and
vfcmp instructions.

[1]:https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640713.html

gcc/ChangeLog:

	PR target/113034
	* config/loongarch/lasx.md (UNSPEC_LASX_XVFCMP_*): Remove.
	(lasx_xvfcmp_caf_<flasxfmt>): Remove.
	(lasx_xvfcmp_cune_<FLASX:flasxfmt>): Remove.
	(FSC256_UNS): Remove.
	(fsc256): Remove.
	(lasx_xvfcmp_<vfcond:fcc>_<FLASX:flasxfmt>): Remove.
	(lasx_xvfcmp_<fsc256>_<FLASX:flasxfmt>): Remove.
	* config/loongarch/lsx.md (UNSPEC_LSX_XVFCMP_*): Remove.
	(lsx_vfcmp_caf_<flsxfmt>): Remove.
	(lsx_vfcmp_cune_<FLSX:flsxfmt>): Remove.
	(vfcond): Remove.
	(fcc): Remove.
	(FSC_UNS): Remove.
	(fsc): Remove.
	(lsx_vfcmp_<vfcond:fcc>_<FLSX:flsxfmt>): Remove.
	(lsx_vfcmp_<fsc>_<FLSX:flsxfmt>): Remove.
	* config/loongarch/simd.md
	(fcond_simd): New define_code_iterator.
	(<simd_isa>_<x>vfcmp_<fcond:fcond_simd>_<simdfmt>):
	New define_insn.
	(fcond_simd_rev): New define_code_iterator.
	(fcond_rev_asm): New define_code_attr.
	(<simd_isa>_<x>vfcmp_<fcond:fcond_simd_rev>_<simdfmt>):
	New define_insn.
	(fcond_inv): New define_code_iterator.
	(fcond_inv_rev): New define_code_iterator.
	(fcond_inv_rev_asm): New define_code_attr.
	(<simd_isa>_<x>vfcmp_<fcond_inv>_<simdfmt>): New define_insn.
	(<simd_isa>_<x>vfcmp_<fcond_inv:fcond_inv_rev>_<simdfmt>):
	New define_insn.
	(UNSPEC_SIMD_FCMP_CAF, UNSPEC_SIMD_FCMP_SAF,
	UNSPEC_SIMD_FCMP_SEQ, UNSPEC_SIMD_FCMP_SUN,
	UNSPEC_SIMD_FCMP_SUEQ, UNSPEC_SIMD_FCMP_CNE,
	UNSPEC_SIMD_FCMP_SOR, UNSPEC_SIMD_FCMP_SUNE): New unspecs.
	(SIMD_FCMP): New define_int_iterator.
	(fcond_unspec): New define_int_attr.
	(<simd_isa>_<x>vfcmp_<fcond_unspec>_<simdfmt>): New define_insn.
	* config/loongarch/loongarch.cc (loongarch_expand_lsx_cmp):
	Remove unneeded special cases.

gcc/testsuite/ChangeLog:

	PR target/113034
	* gcc.target/loongarch/vfcmp-f.c: New test.
	* gcc.target/loongarch/vfcmp-d.c: New test.
	* gcc.target/loongarch/xvfcmp-f.c: New test.
	* gcc.target/loongarch/xvfcmp-d.c: New test.
	* gcc.target/loongarch/vector/lasx/lasx-vcond-2.c: Scan for cune
	instead of cne.
	* gcc.target/loongarch/vector/lsx/lsx-vcond-2.c: Likewise.