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(parent: 0324d23) | patch
target/ppc: PMIs are level triggered
authorNicholas Piggin <npiggin@gmail.com>
Tue, 6 Aug 2024 13:13:14 +0000 (23:13 +1000)
committerNicholas Piggin <npiggin@gmail.com>
Sun, 3 Nov 2024 23:08:32 +0000 (09:08 +1000)
commitc5747965afca017e27a475082126594e8306c766
tree6cfab986d4724b43a66273bbd01506240b04a9b7tree
parent0324d236d2918c18a9ad4a1081b1083965a1433bcommit | diff
target/ppc: PMIs are level triggered

In Book-S / Power processors, the performance monitor interrupts are
driven by the MMCR0[PMAO] bit, which is level triggered and not cleared
by the interrupt.

Others may have different performance monitor architecture, but none of
those are implemented by QEMU.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
target/ppc/excp_helper.c diff | blob | blame | history
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