LoongArch: Fix ICE when trying to recognize bitwise + alsl.w pair [PR119127]

LoongArch: Fix ICE when trying to recognize bitwise + alsl.w pair [PR119127]

When we call loongarch_reassoc_shift_bitwise for
<optab>_alsl_reversesi_extend, the mask is in DImode but we are trying
to operate it in SImode, causing an ICE.

To fix the issue sign-extend the mask into the mode we want.  And also
specially handle the case the mask is extended into -1 to avoid a
miss-optimization.

gcc/ChangeLog:

	PR target/119127
	* config/loongarch/loongarch.cc
	(loongarch_reassoc_shift_bitwise): Sign extend mask to mode,
	specially handle the case it's extended to -1.
	* config/loongarch/loongarch.md
	(loongarch_reassoc_shift_bitwise): Update the comment for the
	special case.