RISC-V: Fix register overlap issue for some xtheadvector instructions

RISC-V: Fix register overlap issue for some xtheadvector instructions

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.

To handle this issue, we add an attribute "spec_restriction" to disable
some alternatives for xtheadvector.

gcc/ChangeLog:

	* config/riscv/riscv.md (none,thv,rvv): New attribute.
	(no,yes): Add an attribute to disable alternative
	for xtheadvector or RVV1.0.
	* config/riscv/vector.md:
	Disable alternatives that destination register overlaps
	source register group for xtheadvector.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>