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[Patch AArch64] Improve SIMD concatenation with zeroes
authorjgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 2 Oct 2015 08:32:12 +0000 (08:32 +0000)
committerjgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 2 Oct 2015 08:32:12 +0000 (08:32 +0000)
commitcf40f9adf04e9bce908a97f131f1d32fb7ee49ae
tree1579edabcb4c2a6726e1893c28ad36ba3493f097tree
parentf431d6bd97fd5d646b79641d9b3c22ebdf192f2dcommit | diff
[Patch AArch64] Improve SIMD concatenation with zeroes

gcc/

* config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>): Add
alternatives for reads from memory and moves from general-purpose
registers.
(*aarch64_combinez_be<mode>): Likewise.

gcc/testsuite/

* gcc.target/aarch64/vect_combine_zeroes_1.c: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228374 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog diff | blob | blame | history
gcc/config/aarch64/aarch64-simd.md diff | blob | blame | history
gcc/testsuite/ChangeLog diff | blob | blame | history
gcc/testsuite/gcc.target/aarch64/vect_combine_zeroes_1.c [new file with mode: 0644] blob
Mirror of https://gcc.gnu.org/git/gcc.git