RISC-V: Short-forward-branch opt for SiFive 7 series cores.

RISC-V: Short-forward-branch opt for SiFive 7 series cores.

	gcc/
	* config/riscv/constraints.md (L): New.
	* config/riscv/predicates.md (lui_operand): New.
	(sfb_alu_operand): New.
	* config/riscv/riscv-protos.h (riscv_expand_conditional_move): Declare.
	* config/riscv/riscv.c (riscv_expand_conditional_move): New.
	* config/riscv/riscv.h (TARGET_SFB_ALU): New.
	* config/riscv/risc.md (type): Add sfb_alu.
	(branch<mode>): Renamed from branch_order<mode>.  Change predicate for
	operand 3 to reg_or_0_operand.  In output string, change %3 to %z3.
	(branch_zero<mode>): Delete.
	(mov<mode>cc): New.
	(mov<GPR:mode><X:mode>cc): Likewise.
	* config/riscv/sifive-7.md (sifive_7_sfb_alu): New.  Use in bypasses.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270758 138bc75d-0d04-0410-961f-82ee72b054a4