RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine

RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine

The vwaddu and vwsubu combine pattern should take plus/minus
instead of any_widen_binop.  This PATCH would like to fix it.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Take concrete op instead
	of any_widen_binop for vwaddu/vwsubu wx combine.

Signed-off-by: Pan Li <pan2.li@intel.com>