RISC-V: Support RVV VFWMUL rounding mode intrinsic API

RISC-V: Support RVV VFWMUL rounding mode intrinsic API

This patch would like to support the rounding mode API for the
VFWMUL for the below samples.

* __riscv_vfwmul_vv_f64m2_rm
* __riscv_vfwmul_vv_f64m2_rm_m
* __riscv_vfwmul_vf_f64m2_rm
* __riscv_vfwmul_vf_f64m2_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(vfwmul_frm_obj): New declaration.
	(vfwmul_frm): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h:
	(vfwmul_frm): Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfwmul_frm): New function definition.
	* config/riscv/vector.md: (frm_mode) Add vfwmul to frm_mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-widening-mul.c: New test.