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[RISC-V][PR target/119971] Avoid losing shift count masking
authorJeff Law <jlaw@ventanamicro.com>
Fri, 27 Jun 2025 13:00:15 +0000 (07:00 -0600)
committerJeff Law <jlaw@ventanamicro.com>
Fri, 27 Jun 2025 13:00:15 +0000 (07:00 -0600)
commitde6124c9e5ed472f567b51fa76f18335cdddbbaf
treef10dabafe3473bcf10f15f80a204e0bacf54cd95tree
parent08bdb6b4a32f1f696862db25fdcc364870b52d82commit | diff
[RISC-V][PR target/119971] Avoid losing shift count masking

Fix typo spotted by Bernhard Reutner-Fischer.

PR target/119971

gcc/testsuite/
* gcc.target/riscv/pr119971.c: Fix typo.
gcc/testsuite/gcc.target/riscv/pr119971.c diff | blob | blame | history
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