RISC-V: Add Types to Un-Typed Risc-v Instructions

RISC-V: Add Types to Un-Typed Risc-v Instructions

Updates risc-v instructions to ensure that no instruction is left
without a type attribute. Added new types "trap" and "cbo" (for
cache related instructions)

Tested for regressions using rv32/64 multilib with newlib/linux and
rv32/64 gcv for linux.

gcc/Changelog:

	* config/riscv/riscv.md: Update/Add types

Reviewed-by: Jeff Law <jlaw@ventanamicro.com>
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>