[RISC-V][PR target/122147] Avoid creating (subreg (mem)) in RISC-V port

[RISC-V][PR target/122147] Avoid creating (subreg (mem)) in RISC-V port

So another fun bug.  Utterly amazed we didn't trip over this in some form or
another until now.

We're generating a (subreg (mem)) expression during combine because
"move_operand" accepts it as a valid operand.  We've discouraged those kinds of
expressions for a long time, even though they're generally expected to act like
registers due to reloading.

In this case reloading just goes into an infinite loop 🙁   Rather than
try to fix this in LRA, let's just avoiding creating the problematical subreg
to begin with.  That's accomplished by being a bit more selective in what
move_operand allows.  I'm not particularly happy with what I saw in
move_operand, but I'm inclined to let it be right now.

Tested on rv32 and rv64.  Bootstraps on the Pioneer and BPI will run later
today.  I'll push once the pre-commit CI system has done its thing.

	PR target/122147
gcc/
	* config/riscv/predicates.md (move_operand): Only allow a REG as the
	operand of a SUBREG.

gcc/testsuite/

	* gcc.target/riscv/pr122147.c: New test.