aarch64: Add vector floating point trunc pattern

aarch64: Add vector floating point trunc pattern

This patch is a follow-up of r15-1079-g230d62a2cdd16c to add vector floating
point trunc pattern for V2DF->V2SF and V4SF->V4HF conversions by renaming the
existing aarch64_float_truncate_lo_<mode><vczle><vczbe> pattern to the standard
optab one, i.e., trunc<Vwide><mode>2<vczle><vczbe>. This allows the vectorizer
to vectorize certain floating point narrowing operations for the aarch64 target.

gcc/ChangeLog:

	* config/aarch64/aarch64-builtins.cc (VAR1): Remap float_truncate_lo_
	builtin codes to standard optab ones.
	* config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_<mode><vczle><vczbe>):
	Rename to...
	(trunc<Vwide><mode>2<vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/trunc-vec.c: New test.

Signed-off-by: Pengxuan Zheng <quic_pzheng@quicinc.com>