]> git.ipfire.org Git - thirdparty/qemu.git/commit
hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5
authorFrederic Konrad <konrad.frederic@yahoo.fr>
Tue, 30 Sep 2025 11:57:18 +0000 (13:57 +0200)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 7 Oct 2025 09:39:15 +0000 (10:39 +0100)
commite836211f7df4b7102f571a33bf01722c9b9bd8b8
tree9fc6a76922260eb2d3f473d70d2f5ac1d9a234b6
parentf51ad36255516a5d41e05734e918b32885923151
hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5

This wires a second GIC for the Cortex-R5, all the IRQs are split when there
is an RPU instanciated.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-id: 20250930115718.437100-4-chigot@adacore.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm/xlnx-zynqmp.c
include/hw/arm/xlnx-zynqmp.h