i386: Optimize strict_low_part QImode insn with high input registers

i386: Optimize strict_low_part QImode insn with high input registers

Following testcase:

struct S1
{
  unsigned char val;
  unsigned char pad1;
  unsigned short pad2;
};

struct S2
{
  unsigned char pad1;
  unsigned char val;
  unsigned short pad2;
};

struct S1 test_add (struct S1 a, struct S2 b, struct S2 c)
{
  a.val = b.val + c.val;

  return a;
}

compiles with -O2 to:

        movl    %edi, %eax
        movzbl  %dh, %edx
        movl    %esi, %ecx
        movb    %dl, %al
        addb    %ch, %al

The insert to %al can go directly from %dh:

        movl    %edi, %eax
        movl    %esi, %ecx
        movb    %dh, %al
        addb    %ch, %al

Patch introduces strict_low_part QImode insn patterns with both of
their input arguments extracted from high register.  This invalid
insn is split after reload to a lowpart insert from the high register
and <insn>qi_ext<mode>_1_slp instruction.

	PR target/78904

gcc/ChangeLog:

	* config/i386/i386.md (*movstrictqi_ext<mode>_1): New insn pattern.
	(*addqi_ext<mode>_2_slp): New define_insn_and_split pattern.
	(*subqi_ext<mode>_2_slp): Ditto.
	(*<any_logic:code>qi_ext<mode>_2_slp): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr78904-8.c: New test.
	* gcc.target/i386/pr78904-8a.c: New test.
	* gcc.target/i386/pr78904-8b.c: New test.
	* gcc.target/i386/pr78904-9.c: New test.
	* gcc.target/i386/pr78904-9a.c: New test.
	* gcc.target/i386/pr78904-9b.c: New test.