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(parent: 0edc246) | patch
target/riscv: convert SiFive E CPU models to RISCVCPUDef
authorPaolo Bonzini <pbonzini@redhat.com>
Thu, 6 Feb 2025 14:32:52 +0000 (15:32 +0100)
committerPaolo Bonzini <pbonzini@redhat.com>
Tue, 20 May 2025 06:18:53 +0000 (08:18 +0200)
commite89d4931d0a15ff0481e9a6e7cbb9f7a28e91434
tree1a9f19e10f0c1c09f39eedb324093ea08af78ae5tree
parent0edc2465ba76c0d2bbeb475b6d2491c92dccd27bcommit | diff
target/riscv: convert SiFive E CPU models to RISCVCPUDef

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/riscv/cpu-qom.h diff | blob | blame | history
target/riscv/cpu.c diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git