RISC-V: Add has compatible check for conflict vsetvl fusion

RISC-V: Add has compatible check for conflict vsetvl fusion

V3: Rebase to trunk and commit it.

This patch fixes SPEC2017 cam4 mismatch issue due to we miss has compatible check
for conflict vsetvl fusion.

Buggy assembler before this patch:

.L69:
	vsetvli	a5,s1,e8,mf4,ta,ma                  -> buggy vsetvl
	vsetivli	zero,8,e8,mf2,ta,ma
	vmv.v.i	v1,0
	vse8.v	v1,0(a5)
	j	.L37
.L68:
	vsetvli	a5,s1,e8,mf4,ta,ma                  -> buggy vsetvl
	vsetivli	zero,8,e8,mf2,ta,ma
	addi	a3,a5,8
	vmv.v.i	v1,0
	vse8.v	v1,0(a5)
	vse8.v	v1,0(a3)
	addi	a4,a4,-16
	li	a3,8
	bltu	a4,a3,.L37
	j	.L69
.L67:
	vsetivli	zero,8,e8,mf2,ta,ma
	vmv.v.i	v1,0
	vse8.v	v1,0(a5)
	addi	a5,sp,56
	vse8.v	v1,0(a5)
	addi	s4,sp,64
	addi	a3,sp,72
	vse8.v	v1,0(s4)
	vse8.v	v1,0(a3)
	addi	a4,a4,-32
	li	a3,16
	bltu	a4,a3,.L36
	j	.L68

After this patch:

.L63:
	ble	s1,zero,.L49
	slli	a4,s1,3
	li	a3,32
	addi	a5,sp,48
	bltu	a4,a3,.L62
	vsetivli	zero,8,e8,mf2,ta,ma
	vmv.v.i	v1,0
	vse8.v	v1,0(a5)
	addi	a5,sp,56
	vse8.v	v1,0(a5)
	addi	s4,sp,64
	addi	a3,sp,72
	vse8.v	v1,0(s4)
	addi	a4,a4,-32
	addi	a5,sp,80
	vse8.v	v1,0(a3)
.L35:
	li	a3,16
	bltu	a4,a3,.L36
	addi	a3,a5,8
	vmv.v.i	v1,0
	addi	a4,a4,-16
	vse8.v	v1,0(a5)
	addi	a5,a5,16
	vse8.v	v1,0(a3)
.L36:
	li	a3,8
	bltu	a4,a3,.L37
	vmv.v.i	v1,0
	vse8.v	v1,0(a5)

Tested on both RV32/RV64 no regression, Ok for trunk ?

	PR target/113429

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Adapt test.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Ditto.