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author	jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
	Mon, 23 Jun 2014 16:00:02 +0000 (16:00 +0000)
committer	jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
	Mon, 23 Jun 2014 16:00:02 +0000 (16:00 +0000)
commit	eb8fdbe9c05d8d23fc667c435e9ce24a6b7d0727
tree	35ccad7b6416801efc000d0cba69c9231567e0e4	tree
parent	519aed8fed9593b553a0017a3eefff45fce7a144	commit \| diff

Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.

gcc/

* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
"yes" where needed.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211899 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog		diff \| blob \| blame \| history
gcc/config/aarch64/aarch64.md		diff \| blob \| blame \| history

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