RISC-V: Support scheduling for sifive p600 series

RISC-V: Support scheduling for sifive p600 series

Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650-670.
Add sifive-p650, sifive-p670 for mcpu option will come in separate patches.

gcc/ChangeLog:

	* config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
	attribute, and include sifive-p600.md.
	* config/riscv/generic-ooo.md: Update type attribute.
	* config/riscv/generic.md: Update type attribute.
	* config/riscv/sifive-7.md: Update type attribute.
	* config/riscv/sifive-p600.md: New file.
	* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
	Add sifive_p600.
	* config/riscv/riscv.cc (sifive_p600_tune_info): New.
	* config/riscv/riscv.h (TARGET_SFB_ALU): Update.
	* doc/invoke.texi (RISC-V Options): Add sifive-p600-series